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| Nios Development Board Cyclone II Edition Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com Development Board Version Document Version Document Date 6XX-40020R 1.3 May 2007 Copyright (c) 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Part Number MNL-N051805-1.3 ii Altera Corporation Contents About this Manual................................................................................... v How to Contact Altera .............................................................................................................................. v Typographic Conventions ...................................................................................................................... vi Chapter 1. Overview Features Overview ................................................................................................................................. 1-1 General Description ............................................................................................................................... 1-1 Factory-Programmed Reference Design ............................................................................................ 1-2 Chapter 2. Board Components Component List ...................................................................................................................................... 2-1 Cyclone II EP2C35 Device (U62) ......................................................................................................... 2-3 Push-Button Switches (SW0 - SW3) .................................................................................................... 2-4 Individual LEDs (D0 - D7) .................................................................................................................... 2-5 Seven-Segment LEDs (U8 & U9) ........................................................................................................ 2-5 SSRAM Chip (U74) ................................................................................................................................ 2-6 DDR SDRAM Chip (U63) ..................................................................................................................... 2-9 Flash Memory (U5) .............................................................................................................................. 2-11 Ethernet MAC/PHY (U4) & RJ45 Connector (RJ1) ........................................................................ 2-13 Serial Connector (J19) ......................................................................................................................... 2-15 Expansion Prototype Connectors (PROTO1 & PROTO2) ............................................................. 2-16 CompactFlash Connector (CON3) .................................................................................................... 2-23 PMC Connector (JH1 & JH2) .............................................................................................................. 2-26 Mictor Connector (J25) ........................................................................................................................ 2-29 Test Points (TP1 - TP8) ....................................................................................................................... 2-31 EPCS64 Serial Configuration Device (U69) ..................................................................................... 2-32 Configuration Controller Device (U3) .............................................................................................. 2-33 Configuration-Status LEDs ........................................................................................................... 2-33 Configuration & Reset Buttons .................................................................................................... 2-34 SW8 - CPU Reset ...................................................................................................................... 2-34 SW9 - Factory Config ............................................................................................................... 2-35 SW10 - Reset, Config ................................................................................................................ 2-35 Reset Distribution ........................................................................................................................... 2-36 Starting Configuration ................................................................................................................... 2-36 Factory & User Configurations .................................................................................................... 2-36 Configuration Process ................................................................................................................... 2-37 Flash Memory Partitions ............................................................................................................... 2-38 User Application Space ............................................................................................................ 2-38 User Configuration ................................................................................................................... 2-39 Factory Configuration .............................................................................................................. 2-39 Persistent Data ........................................................................................................................... 2-39 Altera Corporation iii Contents Nios Development Board Cyclone II Edition JTAG Connectors (J24 & J5) ............................................................................................................... JTAG Connector to FPGA (J24) .................................................................................................... JTAG Connector to EPM7256AE Device (J5) .............................................................................. Clock Circuitry ..................................................................................................................................... Power-Supply Circuitry ...................................................................................................................... 2-39 2-39 2-41 2-41 2-44 Appendix A. Restoring the Factory Configuration Introduction ........................................................................................................................................... A-1 Reprogramming the Flash Memory ................................................................................................... A-1 Reprogramming the EPM7256AE Configuration Controller Device ............................................ A-1 Appendix B. Connecting to the Board via Ethernet Introduction ........................................................................................................................................... Connecting the Ethernet Cable ........................................................................................................... Connecting the LCD Screen ........................................................................................................... Obtaining an IP Address ................................................................................................................ LAN Connection ....................................................................................................................... DHCP .................................................................................................................................... Static IP Address .................................................................................................................. Point-to-Point Connections .................................................................................................... Browsing to Your Board ...................................................................................................................... B-1 B-1 B-2 B-2 B-3 B-3 B-3 B-4 B-5 iv Altera Corporation About this Manual This manual provides details about the Nios(R) development board, CycloneTM II Edition.Nios Development Board Cyclone II Edition The table shows this document's revision history. Date & Revision May 2007, 1.3 Description Corrected Figure 1-1 and Figure 2-21. Revised "How to Contact Altera". Updated headers and footers. Corrected statement: LEDs D0 - D7 turn on when driven to 0, not 1. Updated headers and footers. Updated part numbers to RoHS compliant parts Corrected D7 pin information in LED pin table Removed pin labels from J19 figure Added J19 pin table Changed PROTO1 and PROTO2 figures to use board net names Added PROTO1 and PROTO2 pin tables Corrected FPGA pin label for CON3 pin 9 in PMC Connector pin table Added new pin AE15 to PMC Connector pin table Added U69 pin table Corrected factory config button figure Added pin and device information and corrected net name for U3 Starting Configuration step 3 Improved clock circuitry figure Added clock signal pin tables October 2006, 1.2 June 2006, 1.1 May 2005, 1.0 First publication. How to Contact Altera For the most up-to-date information about Altera products, refer to the following table. Contact Method Website Website Email Contact (1) Technical support Technical training Address www.altera.com/support www.altera.com/training custrain@altera.com Altera Corporation May 2007 v Nios Development Board Cyclone II Edition About this Manual Contact (1) Product literature Altera literature services Non-technical support (General) Contact Method Website Email Email Address www.altera.com/literature literature@altera.com nacomp@altera.com authorization@altera.com (Software Licensing) Email Note to table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions Visual Cue Bold Type with Initial Capital Letters bold type This document uses the typographic conventions shown below. Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: Italic Type with Initial Capital Letters Italic type Initial Capital Letters "Subheading Title" Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: "Typographic Conventions." Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. Courier type 1., 2., 3., and a., b., c., etc. v Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. The checkmark indicates a procedure that consists of one step only. * vi Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 About this Manual Visual Cue 1 c Meaning The hand points to information that requires special attention. The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. The warning indicates information that should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. w r f Altera Corporation May 2007 Reference Manual vii Nios Development Board Cyclone II Edition About this Manual viii Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 1. Overview Features Overview The Nios Development Board, Cyclone II Edition, provides a hardware platform for developing embedded systems based on Altera(R) Cyclone II devices. The Nios Development Board, Cyclone II Edition provides the following features: Nios Development Board Cyclone II EditionA Cyclone II EP2C35F672C5 or EP2C35F672C5N FPGA with 33,216 logic elements (LE) and 483,840 bits of on-chip memory 16 MBytes of flash memory 2 MBytes of synchronous SRAM 32 MBytes of double data rate (DDR) SDRAM On-board logic for configuring the FPGA from flash memory On-board Ethernet MAC/PHY device and RJ45 connector Two 5.0 V-tolerant expansion/prototype headers each with access to 41 FPGA user I/O pins CompactFlash connector for Type I CompactFlash cards 32-bit PMC Connector capable of 33 MHz and 66 MHz operation Mictor connector for hardware and software debug RS-232 DB9 serial port Four push-button switches connected to FPGA user I/O pins Eight LEDs connected to FPGA user I/O pins Dual 7-segment LED display JTAG connectors to Altera devices via Altera download cables 50 MHz oscillator and zero-skew clock distribution circuitry Power-on reset circuitry General Description The Nios development board comes pre-programmed with a Nios II processor reference design. Hardware designers can use the reference design as an example of how to build systems using the Nios II processor and to gain familiarity with the features included. Software designers can use the pre-programmed Nios II processor design on the board to begin prototyping software immediately. This document describes the hardware features of the Nios development board, including detailed pin-out information, to enable designers to create custom FPGA designs that interface with all components on the board. A complete set of schematics, a physical layout database, and GERBER files for the development board are installed with the Nios II development tools in the Altera Corporation May 2007 1-1 Overview f See the Nios II Development Kit, Getting Started User Guide for instructions on setting up the Nios development board and installing Nios II development tools. Figure 1-1shows a block diagram of the Nios development board. Figure 1-1. Nios Development Board, Cyclone II Edition Block Diagram 16 Mbyte DDR SDRAM 50MHz Oscillator 2 Mbyte SSRAM Vccint 1.2-V 5.0 V Regulators Vccio 3.3-V EPCS64 Configuration Device JTAG Connector 27 Mictor Connector Configuration Controller Proto 1 Expansion Prototype Connector Cyclone II EP2C35 FPGA 16 Mbyte Flash Memory Compact Flash 41 Ethernet MAC/PHY RJ45 Connector Proto 2 Expansion Prototype Connector PMC Connector Push-button Switches (4) 4 8 User LEDs (8) 16 Dual Seven-Segment Display RS-232 FactoryProgrammed Reference Design When power is applied to the board, on-board logic configures the FPGA using hardware configuration data stored in flash memory. After successful configuration, the Nios II processor design in the FPGA wakes up and begins executing boot code from flash memory. The board is factory-programmed with a default reference design. This reference design is a web server that delivers web pages via the Ethernet port. For further information on the default reference design, refer to Appendix B: Connecting to the Board via Ethernet. 1-2 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Overview In the course of development, you might overwrite or erase the flash memory space containing the default reference design. Altera provides the flash image for the default reference design so you can return the board to its default state. Refer to Appendix A: Restoring the Factory Configuration for more information. Altera Corporation May 2007 Reference Manual 1-3 Nios Development Board Cyclone II Edition Overview 1-4 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 2. Board Components Component List This section introduces all the important components on the Nios development board. See Figure 2-1 and Table 2-1 for component locations and brief descriptions of all board features. Figure 2-1. Nios Development Board Reset, Config (SW10) J19 RJ1 D34 U5 JH2 TP1- TP8 LED7 LED6 J26 Optional Power Supply PROTO1 (J11, J12, J13) J24 JH1 U4 J5 J27 U69 Y2 J25 PROTO2 (J15, J16, J17) U3 U74 U62 D0 - D7 J4 U63 CPU Reset (SW8) U8 U9 CON3 Factory Config (SW9) SW0 - SW3 Table 2-1. Nios Development Board, Cyclone II Edition Components & Interfaces Board Designation U62 Name Cyclone II FPGA Description EP2C35F672C5 or EP2C35F672C5N device. User Interface SW0 - SW3 D0 - D7 U8, U9 Push-button switches Individual LEDs Seven-segment LEDs Four momentary contact switches for user input to the FPGA. Eight individual LEDs driven by the FPGA. Two seven-segment LEDs that display numeric output from the FPGA. Altera Corporation May 2007 2-1 Board Components Table 2-1. Nios Development Board, Cyclone II Edition Components & Interfaces (Continued) Board Designation Memory U74 U5, LED7 SSRAM memory Flash memory 2 Mbytes of synchronous SRAM. 16 Mbytes of nonvolatile memory for use by both the FPGA and the configuration controller. LED7 lights whenever the flash chip-enable is asserted. 32 Mbytes of DDR SDRAM. Name Description U63 DDR SDRAM memory Connections & Interfaces U4, RJ1 J19 Ethernet MAC/PHY Serial connector 10/100 Ethernet MAC/PHY chip connected to an RJ45 Ethernet connector. RS-232 serial connector with 5 V-tolerant buffers. Supports all RS-232 signals. Expansion headers connecting to 41 I/O pins on the FPGA. Supplies 3.3V and 5.0V for use by a daughter card. Expansion headers connecting to 41 I/O pins on the FPGA. Supplies 3.3V and 5.0V for use by a daughter card. CompactFlash connector for memory expansion. Expansion connector for a PCI mezzanine card. Mictor connector providing access to 27 I/O pins on the FPGA. Allows debugging Nios II systems using a First Silicon Solutions (FS2) debug probe. Test points providing access to eight FPGA I/O pins. JTAG connection to the FPGA allowing hardware configuration using the Quartus(R) II software and software debug using the Nios II IDE. JTAG connection to the MAX(R) configuration controller. Connects to the EPCS serial configuration device for in-system programming. PROTO1 (J11, J12, J13) Expansion prototype connector PROTO2 (J15, J16, J17) Expansion prototype connector CON3 JH1, JH2 J25 CompactFlash connector PMC connector Mictor connector TP1 - TP8 J24 Test Points JTAG connector J5 J27 JTAG connector EPCS configuration header Configuration & Reset U3 U69 SW8 MAX Configuration controller Altera MAX EPM7256AE device used to configure the FPGA from flash memory. Serial configuration device CPU Reset button Altera EPCS64 low-cost serial configuration device to configure the FPGA. Push-button switch to reboot the Nios II processor configured in the FPGA. 2-2 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-1. Nios Development Board, Cyclone II Edition Components & Interfaces (Continued) Board Designation SW9 SW10 LED0 - LED3, LED6 Name Factory Config button Reset, Config Configuration status LEDs Description Push-button switch to reconfigure the FPGA with the factory-programmed reference design. Push-button switch to reset the board. LEDs that display the current configuration status of the FPGA. Clock Circuitry Y2 J4 Oscillator External clock input 50 MHz clock signal driven to FPGA. Connector to FPGA clock pin. Power Supply J26 D34 J28, J29, J30, J33 (and more) DC power jack Bridge rectifier Optional Power Supply 16V DC unregulated power source. Power rectifier allows for center-negative or centerpositive power supplies. External power supply can be connected for highcurrent applications. The sections that follow describe each component in detail. Cyclone II EP2C35 Device (U62) U62 is a Cyclone II FPGA in a 672-pin FineLine BGA(R) package. Depending on the board revision, the part number is EP2C35F672C5 or EP2C35F672C5N. Table 2-2 lists the device features. Table 2-2. Cyclone II EP2C35 Device Features LEs M4K Memory Blocks Total RAM Bits Embedded 18x18 Multiplier Blocks PLLs User I/O Pins 33,216 105 483,840 35 4 475 1 Preproduction builds of the Nios Development Board, Cyclone II Editon have an EP2C35F6728ES device. Altera Corporation May 2007 Reference Manual 2-3 Nios Development Board Cyclone II Edition Board Components The development board provides two separate methods for configuring the FPGA: 1. Using the Quartus(R) II software running on a host computer, a designer configures the device directly via an Altera download cable connected to the FPGA JTAG header (J24). When power is applied to the board, a configuration controller device (U3) attempts to configure the FPGA with hardware configuration data stored in flash memory. For more information on the configuration controller, refer to "Configuration Controller Device (U3)" on page 2-33. 2. f For Cyclone II-related documentation including pin out data for the EP2C35 device, see the Altera Cyclone II literature page at www.altera.com/literature/lit-cyc2.jsp. SW0 - SW3 are momentary-contact push-button switches to provide stimulus to designs in the FPGA. Refer to Figure 2-2. Each switch is connected to an FPGA general-purpose I/O pin with a pull-up resistor as shown in Table 2-3. Each I/O pin perceives a logic 0 when its corresponding switch is pressed. Figure 2-2. Push-Button Switches (SW0 - SW3) D0 D1 D2 D3 D4 D5 D6 D7 Push-Button Switches (SW0 SW3) SW0 SW1 SW2 SW3 Table 2-3. Push Button Switches Pin Table Button SW0 SW1 SW2 SW3 Y11 AA10 AB10 AE6 FPGA Pin Board Net Name user_pb0 user_pb1 user_pb2 user_pb3 2-4 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Individual LEDs (D0 - D7) This Nios development board provides eight individual LEDs connected to the FPGA. Refer to "Push-Button Switches (SW0 - SW3)" on page 2-4. D0 - D7 are connected to general purpose I/O pins on the FPGA as shown in Table 2-4. When a pin drives logic 0, the corresponding LED turns on. Table 2-4. LED Pin Table LED D0 D1 D2 D3 D4 D5 D6 D7 AC10 W11 W12 AE8 AF8 AE7 AF7 AA11 FPGA Pin Board Net Name pld_led0 pld_led1 pld_led2 pld_led3 pld_led4 pld_led5 pld_led6 pld_led7 Seven-Segment LEDs (U8 & U9) U8 and U9 connect to the FPGA, and each segment is individually controlled by a general-purpose I/O pin. Refer to Figure 2-3. When a pin drives logic 0, the corresponding U8 and U9 LED turns on. See Table 2-5 for pin-out details. Figure 2-3. Dual Seven-Segment Display U8 U9 a f g e d dp c e b f a b g c d dp Altera Corporation May 2007 Reference Manual 2-5 Nios Development Board Cyclone II Edition Board Components Table 2-5. Dual Seven-Segment Display FPGA Pin U8 AE13 AF13 AD12 AE12 AA12 Y12 V11 U12 10 9 8 5 4 2 3 7 a b c d e f g dp hex_0A hex_0B hex_0C hex_0D hex_0E hex_0F hex_0G hex_0DP U8 & U9 Pin Pin Function Board Net Name U9 V14 V13 AD11 AE11 AE10 AF10 AD10 AC11 10 9 8 5 4 2 3 7 a b c d e f g dp hex_1A hex_1B hex_1C hex_1D hex_1E hex_1F hex_1G hex_1DP SSRAM Chip (U74) U74 is a 32-bit, 2 Mbyte Cypress SSRAM chip. Depending on the board revision, the part number is CY7C1380C-167AC or CY7C1380D-167AXC. The chip is rated for synchronous accesses up to 167 MHz. U74 connects to the FPGA so it can be used by a Nios II embedded processor as generalpurpose memory. The factory-programmed Nios II reference design identifies the SSRAM devices in its address space as a contiguous 2 Mbyte, 32-bit-wide, zero-wait-state main memory. 2-6 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-6 shows all connections between the FPGA and the SSRAM chip. Table 2-6. SSRAM Pin Table FPGA Pin AB3 AB4 G5 G6 B2 B3 C2 C3 L9 F7 L10 J5 L4 C6 A4 B4 A5 B5 B6 A6 C4 G9 M3 M2 M4 M5 C7 L2 L3 L7 L6 N9 37 36 35 34 33 32 38 39 42 43 44 45 46 47 48 49 50 81 82 99 100 85 93 94 95 96 98 52 53 56 57 58 U74 Pin A0 A1 A2 A3 A4 A5 Pin Function Board Net Name ssram_a0 ssram_a1 ssram_a2 ssram_a3 ssram_a4 ssram_a5 ssram_a6 ssram_a7 ssram_a8 ssram_a9 ssram_a10 ssram_a11 ssram_a12 ssram_a13 ssram_a14 ssram_a15 ssram_a16 ssram_a17 ssram_a18 ssram_a19 ssram_a20 ssram_adsc_n ssram_be_n0 ssram_be_n1 ssram_be_n2 ssram_be_n3 ssram_ce1_n ssram_d0 ssram_d1 ssram_d2 ssram_d3 ssram_d4 NC/A19 NC/A20 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 ADSC_N BE_n0 BE_n1 BE_n2 BE_n3 CE1_n D0 D1 D2 D3 D4 Altera Corporation May 2007 Reference Manual 2-7 Nios Development Board Cyclone II Edition Board Components Table 2-6. SSRAM Pin Table (Continued) FPGA Pin P9 K1 K2 K4 K3 J2 J1 H2 H1 J3 J4 H3 H4 G1 G2 F2 F1 K8 K7 G4 G3 K6 K5 E2 E1 J8 J7 D5 J9 D7 H10 B7 A7 59 62 63 68 69 72 73 74 75 78 79 18 19 22 23 24 25 28 29 2 3 6 7 8 9 12 13 86 87 84 83 97 92 U74 Pin Pin Function D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D24 D25 D26 D27 D28 D29 D30 D31 D16 D17 D18 D19 D20 D21 D22 D23 OE_n WE_n ADSP_n ADV_n CE2 CE3_n Board Net Name ssram_d5 ssram_d6 ssram_d7 ssram_d8 ssram_d9 ssram_d10 ssram_d11 ssram_d12 ssram_d13 ssram_d14 ssram_d15 ssram_d16 ssram_d17 ssram_d18 ssram_d19 ssram_d20 ssram_d21 ssram_d22 ssram_d23 ssram_d24 ssram_d25 ssram_d26 ssram_d27 ssram_d28 ssram_d29 ssram_d30 ssram_d31 ssram_oe_n ssram_we_n ssram_adsp_n ssram_adv_n ssram_ce2 ssram_ce3_n 2-8 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-6. SSRAM Pin Table (Continued) FPGA Pin K9 E5 88 89 U74 Pin Pin Function GW_n CLK Board Net Name ssram_gw_n sram_clk The following pins on U74 have fixed connections, which restricts the usable modes of operation: MODE is pulled low to enable Linear Burst ZZ is pulled low to leave the chip enabled GLOBALW_n is pulled high to disable the global write CE2 and CE3_n are wired high and low respectively to be enabled and to make CE1_n the master chip enable f See www.cypress.com for detailed information about the SSRAM chip. U63 is a Micron DDR SDRAM chip. Depending on the board revision, the part number is MT46V16M16TG or MT46V16M16P-6T. The DDR SDRAM pins are connected to the FPGA as shown in Table 2-7. Altera provides a DDR SDRAM controller that allows a Nios II processor to access the DDR SDRAM device as a large, linearly-addressable memory. DDR SDRAM Chip (U63) Table 2-7. DDR SDRAM Pin Table FPGA Pin R2 R3 R4 P7 P6 T2 T3 R6 W2 W1 U6 U7 U5 Y1 2 4 5 7 8 10 11 13 54 56 57 59 60 62 U63 Pin Board Net Name sdram_dq0 sdram_dq1 sdram_dq2 sdram_dq3 sdram_dq4 sdram_dq5 sdram_dq6 sdram_dq7 sdram_dq8 sdram_dq9 sdram_dq10 sdram_dq11 sdram_dq12 sdram_dq13 Altera Corporation May 2007 Reference Manual 2-9 Nios Development Board Cyclone II Edition Board Components Table 2-7. DDR SDRAM Pin Table (Continued) FPGA Pin V5 V6 P3 W4 U2 AA1 T6 V2 R8 W3 R5 U10 P4 V1 T9 T8 AA2 T10 U3 U9 Y4 U1 R7 Y3 V4 U4 AA6 AA7 63 65 16 51 20 47 29 30 31 32 35 36 37 38 39 40 28 41 42 26 27 22 44 24 23 21 46 45 U63 Pin Board Net Name sdram_dq14 sdram_dq15 sdram_dqs0 sdram_dqs1 sdram_dm0 sdram_dm1 sdram_a0 sdram_a1 sdram_a2 sdram_a3 sdram_a4 sdram_a5 sdram_a6 sdram_a7 sdram_a8 sdram_a9 sdram_a10 sdram_a11 sdram_a12 sdram_ba0 sdram_ba1 sdram_cas_n sdram_cke sdram_cs_n sdram_ras_n sdram_we_n sdram_clk_n sdram_clk_p f See www.micron.com for detailed information. 2-10 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Flash Memory (U5) U5 is an 8-bit, 16 Mbyte AMD flash memory device connected to the FPGA. Depending on the board revision, the part number is AM29LV128M or S29GL128M10TFIR1. Refer to Table 2-8 for connections between the FPGA and the flash memory chip. U5 can be used for two purposes: 1. A Nios II embedded processor implemented on the FPGA can use the flash memory as general-purpose memory and non-volatile storage. The flash memory can hold FPGA configuration data that is used by the configuration controller to load the FPGA at power-up. Refer to "Configuration Controller Device (U3)" on page 2-33 for related information. 2. A Nios II processor design in the FPGA can identify the 16 Mbyte flash memory in its address space, and can program new data (either new FPGA configuration data, Nios II software, or both) into flash memory. The Nios II development software includes subroutines for writing and erasing flash memory. 1 The flash memory device shares address and data connections with the Ethernet MAC/PHY device. Table 2-8. Flash Memory Pin Table FPGA Pin F9 H8 D11 E8 B14 A14 F14 G14 F13 G13 C15 B15 B16 C16 D15 51 31 26 25 24 23 22 21 20 10 9 8 7 6 5 U5 Pin Board Net Name fe_a0 fe_a1 fe_a2 fe_a3 fe_a4 fe_a5 fe_a6 fe_a7 fe_a8 fe_a9 fe_a10 fe_a11 fe_a12 fe_a13 fe_a14 Altera Corporation May 2007 Reference Manual 2-11 Nios Development Board Cyclone II Edition Board Components Table 2-8. Flash Memory Pin Table (Continued) FPGA Pin E15 H15 H16 A17 B17 G15 F15 F16 G16 D8 C8 F10 G10 D9 C9 B8 A8 H17 F17 G17 B18 C17 D17 (1) U5 Pin 4 3 54 19 18 11 12 15 2 35 37 39 41 44 46 48 50 32 34 13 16 53 17 Board Net Name fe_a15 fe_a16 fe_a17 fe_a18 fe_a19 fe_a20 fe_a21 fe_a22 fe_a23 fe_d0 fe_d1 fe_d2 fe_d3 fe_d4 fe_d5 fe_d6 fe_d7 flash_cs_n flash_oe_n flash_rw_n flash_wp_n flash_byte_n (1) flash_ry_by_n Note to Table 2-8: BYTE_n on U5 is pulled low to keep the flash memory in byte mode which restricts the usable modes of operation. The on-board configuration controller makes assumptions about whatresides-where in flash memory. For details refer to "SW10 - Reset, Config" on page 2-35. f See www.amd.com for detailed information about the flash memory device. 2-12 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Ethernet MAC/PHY (U4) & RJ45 Connector (RJ1) The LAN91C111 chip (U4) is a 10/100 Ethernet media access control and physical interface (MAC/PHY) chip. The control pins of U4 are connected to the FPGA so that Nios II systems can access Ethernet networks via the RJ-45 connector (RJ1) as shown in Figure 2-4. The Nios II development tools include hardware and software components that allow Nios II processor systems to communicate with the LAN91C111 Ethernet device. Figure 2-4. Ethernet RJ-45 Connector U4 RJ1 Refer to Table 2-9 for connections between the FPGA and the MAC/PHY device. 1 The Ethernet MAC/PHY device shares both address and data connections with the flash memory. Table 2-9. Ethernet MAC/PHY Pin Table FPGA Pin E26 J17 F18 G18 D18 E18 A19 B19 D20 D14 Y15 AA15 41 43 40 45 38 37 42 46 35 36 34 29 U4 Pin Pin Function Address Enable Synchronous Ready VL Bus Access Local Device IO Char Ready Address Strobe Local Bus Clock Ready/Return Bus Cycle Write/Read Bus Chip Select Interrupt Board Net Name (1) enet_aen enet_srdy_n enet_vlbus_n enet_ldev_n enet_iochrdy enet_ads_n enet_lclk enet_rdyrtn_n enet_cycle_n enet_w_r_n enet_datacs_n enet_intr0 Altera Corporation May 2007 Reference Manual 2-13 Nios Development Board Cyclone II Edition Board Components Table 2-9. Ethernet MAC/PHY Pin Table (Continued) FPGA Pin C25 C24 D26 D25 E20 D16 H8 D11 E8 B14 A14 F14 G14 F13 G13 C15 B15 B16 C16 D15 E15 D8 C8 F10 G10 D9 C9 B8 A8 H11 H12 F11 E10 B9 94 95 96 97 31 32 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 107 106 105 104 102 101 100 99 76 75 74 73 71 U4 Pin Pin Function Byte Enable 0 Byte Enable 1 Byte Enable 2 Byte Enable 3 Read Write Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Address Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Board Net Name (1) enet_be_n0 enet_be_n1 enet_be_n2 enet_be_n3 enet_ior_n enet_iow_n fe_a1 fe_a2 fe_a3 fe_a4 fe_a5 fe_a6 fe_a7 fe_a8 fe_a9 fe_a10 fe_a11 fe_a12 fe_a13 fe_a14 fe_a15 fe_d0 fe_d1 fe_d2 fe_d3 fe_d4 fe_d5 fe_d6 fe_d7 fe_d8 fe_d9 fe_d10 fe_d11 fe_d12 2-14 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-9. Ethernet MAC/PHY Pin Table (Continued) FPGA Pin A9 C10 D10 B10 A10 E12 D12 J13 J14 F12 G12 J10 J11 C11 B11 C12 B12 D6 G11 (1) U4 Pin 70 69 68 66 65 64 63 61 60 59 58 56 55 54 53 51 50 49 48 Pin Function Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Data Line Board Net Name (1) fe_d13 fe_d14 fe_d15 fe_d16 fe_d17 fe_d18 fe_d19 fe_d20 fe_d21 fe_d22 fe_d23 fe_d24 fe_d25 fe_d26 fe_d27 fe_d28 fe_d29 fe_d30 fe_d31 Note to Table 2-9: Nets fe_a0 and fe_a16 to fe_a23 do not connect to U4. f See www.smsc.com for detailed information about the LAN91C111 device. J19 is a standard DB-9 serial connector, and is typically used for communication between the FPGA and a host computer via an RS-232 serial cable. Level-shifting buffer (U52) is used between J19 and the FPGA, because the FPGA device cannot interface to RS-232 voltage levels directly. J19 is able to transmit all RS-232 signals. Alternately, the FPGA design can use only the signals it needs, such as J19's RXD and TXD pins. LEDs are connected to the RXD and TXD signals and visually indicate when data is being transmitted or received. Figure 6 and Table 2-10 show the pin connections between the serial connectors and the FPGA. Serial Connector (J19) Altera Corporation May 2007 Reference Manual 2-15 Nios Development Board Cyclone II Edition Board Components Figure 2-5. Serial Connector J19 Function Direction Connector Pin # GND DTR RXD TXD DCD IN OUT OUT IN 3 5 4 2 1 J19 Connector Pin # Direction Function 6 9 8 7 OUT OUT IN OUT RI CTS RTS DSR Table 2-10. Serial Connector Pin Table FPGA Pin AB15 J22 H21 K22 H19 L19 L23 AC15 3 2 4 1 6 9 8 7 J19 Pin Board Net Name serial_rxd serial_txd serial_dtr serial_dcd serial_dsr serial_ri serial_cts serial_rts Expansion Prototype Connectors (PROTO1 & PROTO2) PROTO1 and PROTO2 are standard-footprint, mechanically-stable connections that can be used (for example) as an interface to a specialfunction daughter card. Headers J11, J12, and J13 collectively form PROTO1, and J15, J16 and J17 collectively form PROTO2. The expansion prototype connector interface includes: 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins on the FPGA. Each signal passes through analog switches to protect the FPGA from 5V logic levels. These analog switches are permanently enabled. The output logic-level on the expansion prototype connector pins is 3.3V. PROTO1 switches: U19, U20, U21, U22 and U25 PROTO2 switches: U27, U28, U29, U30 and U31 2-16 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components A buffered, zero-skew copy of the on-board oscillator output from U2. A buffered, zero-skew copy of the FPGA phase-locked loop (PLL) output. A logic-negative power-on reset signal. Five regulated 3.3V power-supply pins (2A total max load for both PROTO1 & PROTO2). One regulated 5V power-supply pin (1A total max load for both PROTO1 & PROTO2). Numerous ground connections. The PROTO1 expansion prototype connector shares FPGA I/O pins with the CompactFlash connector (CON3). Designs can use either the PROTO1 connector or the CompactFlash connector. 1 Do not connect cards to PROTO1 and CON3 at the same time. Damage to one or both cards might result. f See the Altera web site for a list of available expansion daughter cards that can be used with the Nios development board at www.altera.com/devkits. Table 2-11, Figure 2-6 and Figure 2-7 show connections from the PROTO1 expansion headers to the FPGA. Unless otherwise noted, labels indicate FPGA pin numbers... Table 2-11. PROTO1 Pin Table FPGA Pin J11 U3 pin 56 E25 F24 F23 J21 J20 F25 F26 N18 P18 G23 G24 1 3 4 5 6 7 8 9 10 11 12 13 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 proto1_RESET_n proto1_io0 proto1_io1 proto1_io2 proto1_io3 proto1_io4 proto1_io5 proto1_io6 proto1_io7 proto1_io8 proto1_io9 proto1_io10 PROTO1 Pin Connector Board Net Name Altera Corporation May 2007 Reference Manual 2-17 Nios Development Board Cyclone II Edition Board Components Table 2-11. PROTO1 Pin Table (Continued) FPGA Pin G25 G26 H23 H24 J23 J24 H25 H26 K18 K19 K23 K24 J25 J26 M21 T23 R17 K21 P17 14 15 16 17 18 21 23 25 27 28 29 31 32 33 35 36 37 38 39 PROTO1 Pin J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 J11 Connector Board Net Name proto1_io11 proto1_io12 proto1_io13 proto1_io14 proto1_io15 proto1_io16 proto1_io17 proto1_io18 proto1_io19 proto1_io20 proto1_io21 proto1_io22 proto1_io23 proto1_io24 proto1_io25 proto1_io26 proto1_io27 proto1_cardsel_n proto1_io28 J12 Y22 T18 T17 U26 R19 T19 U20 U21 V26 V25 V24 V23 3 4 5 6 7 8 9 10 11 12 13 14 J12 J12 J12 J12 J12 J12 J12 J12 J12 J12 J12 J12 proto1_io40 proto1_io29 proto1_io30 proto1_io31 proto1_io32 proto1_io33 proto1_io34 proto1_io35 proto1_io36 proto1_io37 proto1_io38 proto1_io39 J13 U2 pin 19 9 J13 proto1_osc 2-18 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-11. PROTO1 Pin Table (Continued) FPGA Pin F21 N26 11 13 PROTO1 Pin J13 J13 Connector Board Net Name proto1_pllclk proto1_clkout Figure 2-6. PROTO1 Expansion Prototype Connector - J11, J12 & J13 J11 Pin 1 J13 J12 Pin 1 Pin 1 Altera Corporation May 2007 Reference Manual 2-19 Nios Development Board Cyclone II Edition Board Components (1) (2) (3) (4) J12 GND proto1_RESET_n proto1_io0 proto1_io2 proto1_io4 proto1_io6 proto1_io8 proto1_io10 proto1_io12 proto1_io14 GND 5 7 9 11 13 15 17 19 proto1_io16 proto1_io17 proto1_io18 proto1_io19 proto1_io21 21 23 25 27 29 3 1 1 3 5 7 9 11 13 14 proto1_io39 12 proto1_io37 10 proto1_io35 8 proto1_io33 6 proto1_io31 4 proto1_io29 2 VCC5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 GND proto1_io1 proto1_io3 proto1_io5 proto1_io7 proto1_io9 proto1_io11 proto1_io13 proto1_io15 proto1_io40 proto1_io30 proto1_io32 proto1_io34 proto1_io36 proto1_io38 Notes to Figure 2-7: (1) Vunreg 1 2 GND GND GND GND GND GND 14 16 18 20 GND GND GND GND 4 6 8 10 12 3 5 7 9 11 13 15 17 19 NC VCC3_3 VCC3_3 J11 NC GND GND GND proto1_io20 GND proto1_io22 proto1_io24 proto1_io25 proto1_io27 proto1_io28 31 33 35 37 39 32 34 36 38 40 proto1_io23 NC proto1_io26 proto1_cardsel_n GND 2-20 Reference Manual Nios Development Board Cyclone II Edition J13 Figure 2-7. PROTO1 Pin Information - J11, J12, & J13 Unregulated voltage from DC power supply. Clk from board oscillator. Clk from FPGA. Clk output from PROTO1 card to FPGA. (2) proto1_osc (3) proto1_pllclk (4) proto1_clkout VCC3_3 VCC3_3 VCC3_3 Altera Corporation May 2007 Board Components Table 2-12, Figure 2-8 and Figure 2-9 show connections from the PROTO2 expansion headers to the FPGA. Unless otherwise noted, the labels indicate FPGA pin numbers. Table 2-12. PROTO2 Pin Table FPGA Pin J16 U3 pin 57 AE24 T21 V22 AF23 AE23 AC22 AB21 AD23 AD22 AC21 AD21 AF22 AE22 V18 W19 U17 U18 AF21 AE21 AB20 AC20 AF20 AE20 AD19 AC19 AA17 AA18 W17 AA20 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 21 23 25 27 28 29 31 32 33 35 36 37 38 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 J16 proto2_RESET_n proto2_io0 proto2_io1 proto2_io2 proto2_io3 proto2_io4 proto2_io5 proto2_io6 proto2_io7 proto2_io8 proto2_io9 proto2_io10 proto2_io11 proto2_io12 proto2_io13 proto2_io14 proto2_io15 proto2_io16 proto2_io17 proto2_io18 proto2_io19 proto2_io20 proto2_io21 proto2_io22 proto2_io23 proto2_io24 proto2_io25 proto2_io26 proto2_io27 proto2_cardsel_n PROTO2 Pin Connector Board Net Name Altera Corporation May 2007 Reference Manual 2-21 Nios Development Board Cyclone II Edition Board Components Table 2-12. PROTO2 Pin Table (Continued) FPGA Pin V17 39 PROTO2 Pin J16 Connector Board Net Name proto2_io28 J15 AE17 AB18 AC18 AF19 AE19 AF18 AE18 AA16 Y16 AC17 AD17 AF17 3 4 5 6 7 8 9 10 11 12 13 14 J15 J15 J15 J15 J15 J15 J15 J15 J15 J15 J15 J15 proto2_io40 proto2_io29 proto2_io30 proto2_io31 proto2_io32 proto2_io33 proto2_io34 proto2_io35 proto2_io36 proto2_io37 proto2_io38 proto2_io39 J17 U2 pin 18 F20 AF14 9 11 13 J17 J17 J17 proto2_osc proto2_pllclk proto2_clkout Figure 2-8. PROTO2 Expansion Prototype Connector - J15, J16 & J17 J16 Pin 1 J17 J15 Pin 1 Pin 1 2-22 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Altera Corporation May 2007 (1) (2) (3) (4) J15 GND proto2_RESET_n proto2_io0 proto2_io2 proto2_io4 proto2_io6 proto2_io8 proto2_io10 proto2_io12 proto2_io14 GND CompactFlash Connector (CON3) 1 3 5 7 9 11 13 14 proto2_io39 12 proto2_io37 10 proto2_io35 8 proto2_io33 6 proto2_io31 4 proto2_io29 2 VCC5 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 GND proto2_io1 proto2_io3 proto2_io5 proto2_io7 proto2_io9 proto2_io11 proto2_io13 proto_2io15 proto2_io40 proto2_io30 proto2_io32 proto2_io34 proto2_io36 proto2_io38 Notes to Figure 2-9: Figure 2-9. PROTO2 Pin Information - J15, J16 & J17 The CompactFlash connector header (CON3) enables hardware designs to access a CompactFlash card. Refer to Figure 2-10. The following two access modes are supported: J17 ATA (hot swappable mode) IDE (IDE hard disk mode) (1) Vunreg 1 2 4 6 8 10 12 14 15 17 19 16 18 20 3 5 7 9 11 13 NC VCC3_3 VCC3_3 GND GND GND GND GND GND GND GND GND GND proto2_io16 proto2_io17 proto2_io18 proto2_io19 proto2_io21 proto2_io22 proto2_io24 proto2_io25 proto2_io27 proto2_io28 21 23 25 27 29 31 33 35 37 39 J16 NC 22 24 26 28 30 32 34 36 38 40 GND GND GND proto2_io20 GND proto2_io23 NC proto2_io26 Unregulated voltage from DC power supply. Clk from board oscillator. Clk from FPGA. Clk output from PROTO2 card to FPGA. (2) proto2_osc (3) proto2_pllclk (4) proto2_clkout VCC3_3 VCC3_3 VCC3_3 proto2_cardsel_n GND Reference Manual 2-23 Nios Development Board Cyclone II Edition Board Components Board Components Figure 2-10. CompactFlash Connector Most pins of CON3 connect to I/O pins on the FPGA. The following pins have special connections: Pin 13 and 38 of CON3 (VCC) are driven by a power MOSFET that is controlled by an FPGA I/O pin. This allows the FPGA to control power to the CompactFlash card for the IDE connection mode. Pin 26 of CON3 (-CD1) is pulled up to 5V through a 10 Kohm resistor. This signal is used to detect the presence of a CompactFlash card; when the card is not present, the signal is pulled high through the pull-up resistor. Pin 41 of CON3 (RESET) is pulled up to 5V through a 10 Kohm resistor, and is controlled by the EPM7256AE configuration controller. The FPGA can cause the configuration controller to assert RESET, but the FPGA does not drive this signal directly. The CompactFlash connector shares several FPGA I/O pins with expansion prototype connector PROTO1. Refer to "Expansion Prototype Connectors (PROTO1 & PROTO2)" on page 2-16 for details on PROTO1. 1 Do not connect cards to PROTO1 and CON3 at the same time. Damage to one or both cards might result. Table 2-13 lists connections between CON3 and the FPGA. Table 2-13. CompactFlash Pin Table FPGA Pin E25 F24 6 47 CON3 Pin Pin Function D7 D8 Board Net Name (1) proto1_io0 proto1_io1 2-24 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-13. CompactFlash Pin Table (Continued) FPGA Pin F23 J21 J20 F25 F26 N18 P18 G23 G24 G25 G26 H23 H24 J23 H25 H26 K18 K24 J25 J26 M21 T23 R17 P17 T18 T17 U26 R19 T19 U20 U21 V26 V25 V24 5 48 4 49 3 27 2 28 23 29 22 30 21 31 35 34 42 37 24 19 20 18 7 45 8 46 10 11 12 14 15 16 17 36 CON3 Pin Pin Function D6 D9 D5 D10 D4 D11 D3 D12 D2 D13 D1 D14 D0 D15 IOWR_n IORD_n IORDY_n INTRQ IOCS16_n A1 A0 A2 CS0_n DASP A10 PDIAG A9 A8 A7 A6 A5 A4 A3 WE_n Board Net Name (1) proto1_io2 proto1_io3 proto1_io4 proto1_io5 proto1_io6 proto1_io7 proto1_io8 proto1_io9 proto1_io10 proto1_io11 proto1_io12 proto1_io13 proto1_io14 proto1_io15 proto1_io17 proto1_io18 proto1_io19 proto1_io22 proto1_io23 proto1_io24 proto1_io25 proto1_io26 proto1_io27 proto1_io28 proto1_io29 proto1_io30 proto1_io31 proto1_io32 proto1_io33 proto1_io34 proto1_io35 proto1_io36 proto1_io37 proto1_io38 Altera Corporation May 2007 Reference Manual 2-25 Nios Development Board Cyclone II Edition Board Components Table 2-13. CompactFlash Pin Table (Continued) FPGA Pin V23 Y22 W16 AE16 AD16 W15 56 (U3) (1) (2) (3) CON3 Pin 43 44 32 9 5 26 41 Pin Function INPACK_n REG_n CS1_n ATA_SEL_n Power supply enable CD1_n RESET# Board Net Name (1) proto1_io39 proto1_io40 cf_cs_n cf_atasel_n cf_power (2) cf_present_n proto1_RESET_n (3) Notes to Table 2-13: Nets proto_io16, proto_io20, and proto_io21 do not connect to CON3. The FPGA I/O pin controls a power MOSFET that supplies 5V VCC to this net. proto1_RESET_n is driven by the EPM7256AE configuration controller device (U3). f For more information on the CompactFlash connector (CON3), see www.compactflash.org and www.molex.com. The PCI mezzanine card (PMC) connector, formed by JH1 and JH2, allows Nios II systems in the FPGA to interface to daughter cards using the standard 32-bit PMC form factor. Refer to Figure 2-11. The PMC connector is capable of 33MHz and 66 MHz, and is configured as the PMC host. w Before connecting a daughter card to the PMC connector, the FPGA must first be configured with a design that includes a PMC interface. Damage to either the FPGA or daughter card can result if the FPGA is not configured correctly. PMC Connector (JH1 & JH2) The factory-programmed Nios II reference design does not include a PMC interface. 2-26 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Figure 2-11. PMC Connector Pin 1 Pin 1 JH1 JH2 The PMC connector supplies +3.3V, +5V and +/- 12V, as required by the PCI specification. However, DC power regulators for these supplies cannot provide enough power to fully satisfy the PCI power specification. The current that the board can supply through JH1 and JH2 is dependent on the design configured in the FPGA. As a general guideline, if the PMC card power requirements exceed the specifications shown in Table 2-14, you must connect an external power source. Table 2-14. PMC Card Power Specifications DC Supply +3.3V +5V +12V -12V Maximum Power 9.5 Watts 15 Watts 45 Watts 1.2 Watts J29 J28 J31 Apply External Power Source TP13 w When connecting an external power supply, the fuse for the corresponding voltage should be removed to prevent the two power supplies from interfering with each other. Refer to "Power-Supply Circuitry" on page 2-44 for more information. Table 2-15 lists the connections between the PMC connector and the FPGA. Table 2-15. PMC Connector Pin Table FPGA Pin L20 L21 JH1 & JH2 Pin 61 60 Connector JH1 JH1 Board Net Name pmc_ad0 pmc_ad1 Altera Corporation May 2007 Reference Manual 2-27 Nios Development Board Cyclone II Edition Board Components Table 2-15. PMC Connector Pin Table (Continued) FPGA Pin L24 L25 M19 M22 M23 R24 U22 U25 W21 W23 W24 W25 Y21 Y23 Y24 Y25 Y26 AA23 AA24 AA25 AA26 AB23 AB24 AB25 AB26 AC23 AC25 AC26 AD24 AD25 R20 T22 T24 T25 JH1 & JH2 Pin 59 58 55 54 53 51 49 49 48 48 47 46 45 46 31 32 29 29 28 28 27 26 23 23 22 22 21 20 19 20 52 43 32 26 Connector JH1 JH1 JH1 JH1 JH1 JH2 JH2 JH1 JH2 JH1 JH1 JH2 JH2 JH1 JH2 JH1 JH2 JH1 JH2 JH1 JH1 JH2 JH2 JH1 JH2 JH1 JH1 JH2 JH2 JH1 JH1 JH2 JH2 JH1 Board Net Name pmc_ad2 pmc_ad3 pmc_ad4 pmc_ad5 pmc_ad6 pmc_ad7 pmc_ad8 pmc_ad9 pmc_ad10 pmc_ad11 pmc_ad12 pmc_ad13 pmc_ad14 pmc_ad15 pmc_ad16 pmc_ad17 pmc_ad18 pmc_ad19 pmc_ad20 pmc_ad21 pmc_ad22 pmc_ad23 pmc_ad24 pmc_ad25 pmc_ad26 pmc_ad27 pmc_ad28 pmc_ad29 pmc_ad30 pmc_ad31 pmc_be_n0 pmc_be_n1 pmc_be_n2 pmc_be_n3 2-28 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-15. PMC Connector Pin Table (Continued) FPGA Pin T20 W26 U24 U23 R25 P24 P23 M20 Y14 AA13 Y13 G22 N24 N23 M25 M24 N20 K26 K25 AE15 JH1 & JH2 Pin 43 13 39 42 37 38 36 4 5 6 9 13 33 35 25 16 17 40 47 64 Connector JH1 JH1 JH2 JH2 JH1 JH2 JH1 JH1 JH1 JH1 JH1 JH2 JH1 JH2 JH2 JH1 JH1 JH1 JH2 JH1 Board Net Name pmc _par pmc_clk pmc_perr_n pmc_serr_n pmc_devsel_n pmc_stop_n pmc_irdy_n pmc_inta_n pmc_intb_n pmc_intc_n pmc_intd_n pmc_reset_n pmc_frame_n pmc_trdy_n pmc_idsel pmc_gnt_n pmc_req_n pmc_lock_n pmc_m66en pmc_req64_n Mictor Connector (J25) The Mictor connector (J25) can be used to transmit up to 27 high-speed I/O signals with very low noise via a shielded Mictor cable. J25 can be used as a debug port for the Nios II processor or as a general-purpose I/O connector to the FPGA. Twenty five of the Mictor connector signals are used as data, and two signals are used as clock input and clock output. Most pins on J25 connect to I/O pins on the FPGA (U62). For systems that do not use the Mictor connector for debugging the Nios II processor, any on-chip signals can be routed to I/O pins and probed at J25. External scopes and logic analyzers can connect to J25 and analyze a large number of signals simultaneously. f For details on Nios II debugging products that use the Mictor connector, see www.altera.com. Altera Corporation May 2007 Reference Manual 2-29 Nios Development Board Cyclone II Edition Board Components Figure 2-12 shows an example of an in-target system analyzer ISANios/T by First Silicon Solutions (FS2) Inc. connected to the Mictor connector. For details, see www.fs2.com. Figure 2-12. An ISA-Nios/T Connecting to the Mictor Connector (J25) J25 Five of the signals connect to both the JTAG pins on the FPGA (U62), and the FPGA's JTAG connector (J24). The JTAG signals have special usage requirements. J25 and J24 cannot be used at the same time. Figure 2-13 below shows connections from the Mictor connector to the FPGA. Figure 2-13. Mictor Connector Signaling JTAG Connector Mictor Connector (J25) (J24) FPGA (U62) 5 40 2-30 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Table 2-16 shows the pin out information for J25. Unless otherwise noted, labels indicate FPGA pin numbers. Table 2-16. Mictor Connector Pin Table FPGA Pin V21 AC8 AD8 W10 Y10 V10 V9 AD6 AD7 AE5 AF5 AD4 AD5 AC5 AC6 AF4 AE4 B21 B22 A22 A23 B23 D21 C21 C22 C23 B25 5 38 36 34 32 30 28 26 24 22 20 18 16 10 8 37 35 33 31 29 27 25 23 13 9 7 6 J25 Pin mictor0 mictor1 mictor2 mictor3 mictor4 mictor5 mictor6 mictor7 mictor8 mictor9 Board Net Name mictor_clk mictor10 mictor11 mictor12 mictor13 mictor14 mictor15 mictor16 mictor17 mictor18 mictor19 mictor20 mictor21 mictor22 mictor23 mictor24 mictor_trclk Test Points (TP1 - TP8) TP1 - TP8 are test points connected to I/O pins on the FPGA. FPGA designs can route signals to these I/O pins to be probed. TP1 -TP8 also connect to the configuration controller (U3). Altera Corporation May 2007 Reference Manual 2-31 Nios Development Board Cyclone II Edition Board Components Table 2-17 lists the connections between the FPGA, U3, and the test points. Table 2-17. Test Point Pin Table Test Point TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 FPGA Pin D19 C19 A20 B20 K16 J16 K17 J18 75 76 77 78 79 80 81 83 CPLD Pin Board Net Name pld_user0 pld_user1 pld_user2 pld_user3 pld_user4 pld_user5 pld_user6 pld_user7 EPCS64 Serial Configuration Device (U69) U69 is a serial configuration device connected to the FPGA. Serial configuration devices are flash memory devices with a serial interface which can store configuration data, and load the data into the FPGA upon power up or reconfiguration. U69 can store FPGA configuration data, or Nios II program data, or both. Table 2-18 lists the connections between U69 and the FPGA. Table 2-18. EPCS64 Pin Table FPGA Pin N6 N3 D3 E3 16 8 7 15 U69 Pin Board Net Name pld_dclk pld_data0 pld_cs_n pld_asdo The SOPC Builder EPCS Serial Flash Controller component enables Nios II processor systems to access the EPCS device. Nios II processor systems can read program code or data from the device, and can write new data into the EPCS device. U69 is blank by default. The Quartus II software can program FPGA configuration data (a .pof file) into U69 through an Altera download cable connected to J27. Alternately, software running on a Nios II processor design can write configuration data to U69. 2-32 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components 1 The orientation of J27 is the reverse of J24. f See the Serial Configuration Devices chapter in Altera's Configuration Device Handbook for more information about the EPCS64 device. See the EPCS Device Controller Core with Avalon Interface chapter in the Quartus II Handbook, Volume 5: Altera Embedded Peripherals for information about the EPCS serial flash controller component in SOPC Builder. Configuration Controller Device (U3) The configuration controller (U3) is an Altera MAX 7000 EPM7256AE device. It comes preprogrammed with logic for managing board reset conditions and configuring the FPGA from data stored in flash memory and the EPCS64 serial configuration device (U69). FPGA configuration data files are generated by the Quartus II software. The Nios II integrated development environment (IDE) can write new configuration data to the board's flash memory. f For complete details on the configuration controller connections, see the board schematic. For detailed information about the Altera EPM7256AE device, see the MAX 7000 family literature at www.altera.com/literature/lit-m7k.html. For details on programming configuration data to flash memory, see the Nios II Flash Programmer User Guide, or refer to the Nios II IDE help system. Configuration-Status LEDs The configuration controller is connected to four status LEDs that show the configuration status of the board at a glance as shown in Figure 2-14. The LEDs indicate which configuration, if any, was loaded into the FPGA at power-on as shown in Table 2-19. Figure 2-14. LED1 - LED 4 FPGA Config LED 3 Loading LED 4 Error LED 1 User LED 2 Factory SW9 Factory Config Altera Corporation May 2007 Reference Manual 2-33 Nios Development Board Cyclone II Edition Board Components Table 2-19. Configuration Status LED Indicators LED LED3 LED4 Led Name Loading Error Color Green Red Description This LED blinks while the configuration controller is actively transferring data from flash memory into the FPGA. If this LED is on, then configuration was not transferred from flash memory into the FPGA. This can happen if, for example, the flash memory contains either a valid user or factory configuration. This LED turns on when the user configuration is being transferred from flash memory and stays illuminated when the user configuration data is successfully loaded into the FPGA. If the FPGA was successfully configured by the EPCS64, LED1 will blink slowly. This LED turns on when the factory configuration is being transferred from flash memory and stays illuminated if the factory configuration was successfully loaded into the FPGA. This LED is an indicator of the CONFIG_DONE_signal from the FPGA. This LED illuminates when FPGA configuration completes successfully and CONFIG_DONE goes high. This LED is an indicator of the flash_CE_n line. It illuminates when the flash is being accessed and the CE_n line is being asserted. LED1 User Green LED2 Factory Amber LED6 LED6 Red LED7 LED7 Red Configuration & Reset Buttons The Nios development board uses dedicated switches SW8, SW9 and SW10 for the following fixed functions: SW8 - CPU Reset When SW8 is pressed, a logic-0 is driven onto the FPGA I/O pin C5 (DEV_CLRn). The result of pressing SW8 depends on how the FPGA is configured. Refer to Figure 2-15. The factory-programmed Nios II reference design treats SW8 as a CPUreset button. The Nios II reference design resets and starts executing code from its reset address when SW8 is pressed. 2-34 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Figure 2-15. CPU Reset Button SW8 CPU Reset SW9 - Factory Config Pressing Factory Config (SW9) commands the configuration controller to reconfigure the FPGA with the factory configuration. Refer to Figure 2-16. Figure 2-16. Factory Config Button SW9 Factory Config SW10 - Reset, Config Reset, Config (SW10) is the power-on reset button. Refer to Figure 2-17. When SW10 is pressed, a logic 0 is driven to the power on reset controller (U18). Refer to "Power-Supply Circuitry" on page 2-44 for more details. Whenever SW10 is pressed, the configuration controller attempts to reconfigure the FPGA. Altera Corporation May 2007 Reference Manual 2-35 Nios Development Board Cyclone II Edition Board Components Figure 2-17. Reset, Config Button SW10 Reset, Config Reset Distribution The EPM7256AE device takes a power-on reset pulse from the Linear Technologies 1326 power-sense/reset-generator chip (U18) and distributes it (through internal logic) to other reset pins on the board, that include the following: LAN91C111 (Ethernet MAC/PHY) reset Flash memory reset CompactFlash reset Reset signals delivered to the expansion prototype connectors (PROTO1 & PROTO2) Starting Configuration The following four methods start a configuration sequence: 1. 2. 3. Board power-on Pressing the Reset, Config button (SW10). Asserting (driving 0 volts on) the pld_reconfigreq_n input pin of the EPM7256AE device (U3 pin 94) from the FPGA (U62 pin AA14). Pressing the Factory Config button (SW9). 4. Factory & User Configurations The configuration controller can manage two separate FPGA configurations stored in flash memory U5. These two configurations are referred to as the factory configuration and the user configuration. A 2-36 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components Nios II reference design is factory-programmed into the factory configuration region of the flash memory. In addition, the FPGA can be configured by the EPCS64 serial configuration device. Configuration Process At power-up or reset, the configuration controller attempts to configure the FPGA with data from one of three sources, in the following order: 1. 2. 3. The EPCS64 serial configuration device The user configuration from flash memory The factory configuration from flash memory First, the configuration controller puts the FPGA in active serial (AS) configuration mode. The FPGA then attempt to read configuration data from the EPCS64. If the FPGA finishes configuration successfully, the configuration controller stops. If configuration from the EPCS64 does not succeed, the configuration controller puts the FPGA into passive serial (PS) mode and attempts to load the user configuration from flash memory. If this also fails (because the user configuration is either invalid or not present), the configuration controller attempts to load the factory configuration from flash memory. When SW9 (Factory Config) is pressed, the configuration controller ignores the user configuration and EPCS64, and configures the FPGA with the factory configuration. SW9 provides an escape from a situation in which a valid-but-nonfunctional design is present in user flash memory or the EPCS64. Altera Corporation May 2007 Reference Manual 2-37 Nios Development Board Cyclone II Edition Board Components Flash Memory Partitions The configuration controller expects user and factory configuration data to be stored at fixed locations (offsets) in flash memory. In addition, the factory-programmed reference design expects Nios II software and data to exist at certain locations in flash memory. Table 2-20 shows the expected flash memory partitioning. Table 2-20. Flash Memory Partitions Offset 0x00000000 - 0x00BFFFFF 0x00C00000 - 0x00CFFFFF 0x00D00000 -0x00DFFFFFF 0x00E00000 - 0x00EFFFFF 0x00F00000 - 0x00FAFFFF 0x00FB0000 - 0x00FEFFFF 0x00FF0000 - 0x00FFFFFF Usage User Application Space (11 MB) User Configuration (1 MB) Free Space (1 MB) Factory Configuration (1 MB) Web Pages Web Server Software Persistent Data Factory-Programmed Content Nios II Processor Reference Design Web Pages Web Server Software Network Settings for Web Server 1 This partitioning scheme is merely a convention used by the configuration controller and the factory-programmed reference design. Custom FPGA designs can use the flash memory space in any way necessary. Altera recommends that you do not overwrite the factoryprogrammed flash memory contents. Without a valid factory configuration, the configuration controller may not be able to successfully configure the FPGA. If you alter the factory configuration, you can restore the board to its factoryprogrammed state. Refer to Appendix B: Restoring the Factory Configuration. c User Application Space The lower 11 MB of flash memory is the user application space. This is free space for user designs to store code and data for Nios II programs. The Nios II IDE allows you to compile Nios II programs and program them into the user application space. 2-38 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components User Configuration The user configuration partition is 1 MB, starting at offset 0x00C00000. This section contains the FPGA configuration data for the user configuration. Nios II development tools include documentation on how to create your own user configuration image and program it into flash memory. Factory Configuration The factory configuration partition is 1 MB, starting at offset 0x00E00000. This section contains the FPGA configuration data for the factory configuration. The Nios II processor system in the factory configuration is designed to start executing code from offset 0x00000000 in the flash memory. The Nios II development tools include the source files for the factory programmed hardware and software reference designs. Persistent Data The persistent data partition is 64 KB, starting at offset 0x00FF0000. This partition is for maintaining nonvolatile settings and data, such as the MAC address and IP address for the factory-programmed web server reference design. Persistent data is technically no different than other application data, but it is often convenient to think of certain data as independent from the user hardware or software. JTAG Connectors (J24 & J5) The Nios development board has two 10-pin JTAG headers (J24 and J5) compatible with Altera download cables, such as the USB-BlasterTM. On the Nios development board, each JTAG header connects to one Altera device and forms a single-device JTAG chain. J24 connects to the FPGA (U62), and J5 connects to the EPM7256AE device (U3). JTAG Connector to FPGA (J24) J24 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the FPGA (U62) as shown in Figure 2-18. Altera Quartus II software can directly configure the FPGA with a new hardware image via an Altera download cable as shown in Figure 2-19. In addition, the Nios II IDE can access the Nios II processor JTAG debug module via a download cable connected to the J24 JTAG connector. Altera Corporation May 2007 Reference Manual 2-39 Nios Development Board Cyclone II Edition Board Components Figure 2-18. JTAG Connector (J24) to Cyclone II Device To Mictor Connector (J25) JTAG Signals JTAG Connector (J24) TDI TMS TCK TDO TRST FPGA (U62) Figure 2-19. USB Blaster Connected to J24 JTAG Connector Pin 1 J24 The FPGA's JTAG pins can also be accessed via the Mictor connector (J25). The pins of J24 are connected directly to pins on J25, and care must be taken so that signal contention does not occur between the two connectors. 2-40 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components JTAG Connector to EPM7256AE Device (J5) J5 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the EPM7256AE device (U3). Altera Quartus II software can perform insystem programming (ISP) to reprogram the EPM7256AE device (U3) with a new hardware image via an Altera download cable as shown in Figure 2-20. 1 The orientation of J5 is rotated 180 degrees compared to J24. Most users never need to reprogram the configuration controller design in the EMP7256AE device. Reprogramming the configuration controller can result in an inoperable development board. f To restore the board to its factory-programmed condition, see Appendix B: Restoring the Factory Configuration. Figure 2-20. JTAG Connector (J5) to MAX Device J5 Pin 1 Clock Circuitry The Nios development board includes a 50 MHz free-running oscillator (Y2) and a zero-skew, point-to-point clock distribution network that drives the FPGA (U62), the EPM7256AE configuration controller device (U3), and pins on the PROTO1 & PROTO2 connectors. The zero-skew buffer (U2) drives the clock distribution network using the free-running 50 MHz clock. Refer to Figure 2-21. Altera Corporation May 2007 Reference Manual 2-41 Nios Development Board Cyclone II Edition Board Components Figure 2-21. Clock Circuitry sdram_CLK_p osc_CLK0 osc_CLK1 sram_CLKIN sdram_CLKIN mictor_CLK Mictor (J25) sdram_CLK_n DDR SDRAM (U63) sram_CLK SSRAM (U74) Oscil ator (Y2) SMA External Input (J4) Clock Buffer (U2) FPGA (U62) PLLs PMC_CLK PMC (JH1 & JH2) proto1_PLLCLK proto1_CLKOUT proto1_OSCCLK proto2_PLLCLK proto2_CLKOUT proto2_OSCCLK PROTO2 PROTO1 cpld_CLKOSC MAX (U3) Note to Figure 2-21: (1) To use an external clock signal, remove the crystal oscillator from its socket. Make sure to note the correct orientation of the oscillator before removing it. 2-42 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Board Components The FPGA receives clock input from buffer U2, and from the PROTO1 and PROTO2 connectors, as shown in Table 2-21. Table 2-21. FPGA Clock Input Pin Table FPGA Pin B25 N26 AF4 P25 AC13 N2 B13 FPGA Pin Name IO CLK5 CLK13 CLK6 CLK15 CLK0 CLK8 PLL N/A PLL2 PLL4 PLL2 PLL4 PLL1 PLL3 Signal Source J25 pin 6 J13 pin 13 J17 pin 13 U2 pin 2 U2 pin 3 U2 pin 4 U2 pin 6 Board Net Name mictor_TRCLK proto1_CLKOUT proto2_CLKOUT osc_CLK0 osc_CLK1 sram_CLKIN sdram_CLKIN The FPGA can synthesize new clock signals internally using on-chip PLLs, and drive the clocks to various components on the board, as shown in Table 2-22. Table 2-22. FPGA Clock Output Pin Table FPGA Pin AA7 AA6 E5 W26 F21 F20 V21 (1) FPGA Pin Name PLL1_OUTp PLL1_OUTn PLL3_OUTp IO PLL2_OUTp PLL2_OUTn PLL4_OUTp PLL (1) PLL1 PLL1 PLL3 N/A PLL2 PLL2 PLL4 Signal Destination U63 pin 45 U63 pin 46 U74 pin 89 JH1 pin 13 J13 pin 11 J17 pin 11 J25 pin 5 Board Net Name sdram_CLK_p sdram_CLK_n sram_CLK pmc_CLK proto1_PLLCLK proto2_PLLCLK mictor_CLK Note to Table 2-22: PLLs are only dedicated when using the Enhanced PLL. If you use the Fast PLL, the PLL inputs and outputs are interchangeable. For more information on using PLLs in the Cyclone II refer to the data sheet. The 50 MHz oscillator (Y2) is socketed and can be changed or removed by the user. To drive the clock circuitry using the external clock connector (J4), remove Y2. 1 The factory-programmed configuration controller and Alteraprovided reference designs work only with the 50 MHz clock. Altera Corporation May 2007 Reference Manual 2-43 Nios Development Board Cyclone II Edition Board Components Power-Supply Circuitry The Nios development board runs on a 16V, unregulated, input power supply connected to J26. On-board circuitry generates +/-12V, +5V, +3.3V, +2.5V, and +1.2V regulated power levels. For applications requiring high current, separate voltage levels can be supplied from a workbench power supply. The input power-supply on J26 can be either center-negative or center-positive. A bridge rectifier (D34) presents the appropriate polarity to the voltage regulators. The 5V supply is presented on pin 2 of J12 and J15 for use by any device plugged into the PROTO1 & PROTO2 expansion connectors. The 3.3V supply is used as the power source for all FPGA I/O pins. The 3.3V supply is also available for PROTO1 & PROTO2 daughter cards. The 2.5V supply is used only as the power supply for the DDR SDRAM chip and is not available on any connector or header. The 1.2V supply is used only as the power supply for the Cyclone II device core (VCCINT) and it is not available on any connector or header. The +/-12V supply is provided for the PMC connectors JH1 and JH2. Refer to "PMC Connector (JH1 & JH2)" on page 2-26 for more details. When workbench power supplies are connected to the board, a corresponding fuse must be removed to decouple the on-board voltage regulator. Each on-board regulator drives power through a 7A fuse. Refer to Table 2-23. Table 2-23 lists the details of what voltage levels can be supplied to what points on the board. Table 2-23. Power Supply and Fuse Details Voltage 1.2V 1.2V 1.25V 1.25V 2.5V 3.3V 5V +12V -12V J30 TP12 TP10 TP9 TP11 J29 J28 J31 TP13 Pad F3 F7 F5 F4 F6 F2 F1 F8 F9 Fuse Core power for FPGA. FPGA PLL power supply. DDR SDRAM I/O VTT. DDR SDRAM I/O VREF. Note DDR SDRAM VDD power supply. FPGA VCCIO for pins that interface to DDR SDRAM. 3.3V power for multiple components on the board. 5.0V power for multiple components on the board. Power for the PMC connectors. Power for the PMC connectors. 2-44 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Appendix A. Restoring the Factory Configuration Introduction To restore the factory configuration, you must reprogram the flash memory on the board, and you must Nios Development Board Cyclone II Edition the EPM7256AE configuration controller device. Nios II Embedded Design Suite provides the files required for this operation in the directory Reprogramming the Flash Memory To reprogram the flash memory on the development board, perform the following steps: 1. Open a Nios II command shell. On a Windows PC, click Windows Start, point to Programs, Altera, Nios II EDS Reprogramming the EPM7256AE Configuration Controller Device If the configuration controller design was modified, you must also reprogram the EMP7256AE device (U3). To reprogram the EMP7256AE configuration controller, perform the following steps: 1. Move the programming cable from J24 to J5, labeled "For U3". 1 The orientation of J5 is opposite that of J24. When properly connected to J5, the programming cable lies naturally over the clock oscillator and the dual seven-segment display. Altera Corporation May 2007 A-1 2. Launch the Quartus II software, and click Programmer on the Tools menu. Click Add File and select the following programming file: 3. 4. 5. Your board is now reconfigured to the default factory condition. A-2 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 Appendix B. Connecting to the Board via Ethernet Introduction The Nios development board is factory-programmed with a reference design that implements a web server, among other functions as shown in Figure B-1. This chapter describes how to connect a host computer to the board's Ethernet port, assign an IP address to the board, and browse to the web server from the host computer. Figure B-1. Web Server Reference Design Connecting the Ethernet Cable The Nios II development kit includes an Ethernet (RJ45) cable and a male/female RJ45 crossover adapter. Before you connect these components, you must decide how you want to use the network features of your board. Select one of the two following connection methods: 1. LAN Connection -- To use your Nios development board on a LAN (for example, connecting to an Ethernet hub) do the following: a. Connect one end of the RJ45 cable to the Ethernet connector on the development board (RJ1). Altera Corporation May 2007 B-1 b. Connect the other end to your LAN connection (hub, router, wall plug, etc.). 2. Point-to-Point Connection -- To use your Nios development board connected directly to a host computer point-to-point (not on a LAN), do the following: a. Connect one end of your RJ45 cable to the female socket in the crossover adapter and insert the male end of the crossover adapter into RJ1 on the Nios development board as shown in Figure B-2. Figure B-2. Point-to-Point Connection RJ1 b. Connect the other end of the RJ45 connector directly to the network (Ethernet) port on your host computer. Connecting the LCD Screen The Nios II development kit includes a two-line x 16-character LCD text screen. The web-server software displays useful status and progress messages on this display. If you wish to use the network features of the board, connect the LCD screen to expansion prototype connector J12. Refer to the Nios II Development Kit, Getting Started User Guide for details. Obtaining an IP Address In order to function on a network (either LAN or point-to-point), your board must have an IP address. This section describes the methods to assign an IP address to your board. B-2 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 LAN Connection If you have connected your board to a LAN, the board will either obtain a dynamic IP address using DHCP, or a static IP address stored in flash memory. If you do not know whether or not your LAN supports DHCP, it is easiest to try DHCP first. DHCP Upon reset, the web server attempts to acquire an IP address via the DHCP protocol. The board continues to attempt DHCP self-configuration for two minutes. You can determine if DHCP has succeeded, or if it is still in progress, by reading status messages on the LCD screen. If your LAN does not support DHCP then DHCP configuration ultimately fails, and the web server defaults to a static IP address. If DHCP succeeds, the board displays a success message and the IP address on the LCD screen. The web server is now ready to display web pages. See "Browsing to Your Board" on page B-5 to continue. Static IP Address If the DHCP process fails, the board uses a static IP address stored in flash memory. You need to obtain a safe IP address in your LAN's subnet from your system administrator. Once you know a safe IP address, you can assign it to your board using the steps below. These steps send IP configuration data to the board via an Altera JTAG download cable, such as the USB-Blaster cable. 1. Install the Nios II development tools, connect the JTAG download cable, and apply power to the board, as described in the Nios II Development Kit, Getting Started User Guide. Open a Nios II command shell. On Windows PCs, On a Windows PC, click Windows Start, point to Programs, Altera, Nios II EDS 2. 3. 4. Altera Corporation May 2007 Reference Manual B-3 Nios Development Board Cyclone II Edition 5. Press the ! key to abort the DHCP process and display a prompt. If you don't abort the DHCP process, it will fail after two minutes, and eventually a prompt will appear. 1 The monitor's prompt is the + character. You can enter h 6. At the prompt, type xip: 7. Type xdhcp:off 8. 9. The web server is now ready to display pages using the IP address you assigned. See "Browsing to Your Board" on page B-5 to continue. Point-to-Point Connections All boards are factory programmed with a default IP address of 10.0.0.51 stored in flash memory. The 10.0.0.x subnet is conventionally reserved for development, test, and prototyping. If DHCP fails or is aborted, the board uses this static IP address. The LCD screen displays status messages to indicate when the web server starts running using the default IP address. Your host computer and the development board are the only two devices connected to this simple point-to-point network. For most host operating systems, it is necessary to assign your host computer an IP address on the same subnet as the board. For example, the address 10.0.0.1 will work fine. Any address in the 10.0.0.x subnet will work, and there is no possibility of conflicting with another device on the network. After B-4 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 modifying the host computer's IP address, your computer is ready to connect to the web server. Refer to "Browsing to Your Board" on page B-5 to continue. If you don't have the ability to change the IP address of your host computer, you can change the IP address of the board to match the subnet of the host computer. For example, if your computer's IP address is 1.2.3.4, then you can assign the address 1.2.3.5 to your board. To change the board IP address, follow the steps in "Static IP Address " on page B-3. Every time you reset the board, the web server will attempt to obtain an IP address via DHCP, which takes two minutes to time out. You can abort the DHCP process, or disable DHCP entirely by using the steps in "Static IP Address " on page B-3. Browsing to Your Board Once your board has a valid IP address (obtained from either DHCP selfconfiguration or from flash memory), you can access the board via a web browser (e.g., Microsoft Internet Explorer). To browse to this site, open a web browser and type the IP address of the board (four numbers separated by decimal-points) as a URL directly into the browser's Address input field. You can determine your board's IP address by reading the messages displayed on the LCD screen. Altera Corporation May 2007 Reference Manual B-5 Nios Development Board Cyclone II Edition B-6 Reference Manual Nios Development Board Cyclone II Edition Altera Corporation May 2007 |
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